The increasing gap between market demands, processing architectures complexity and emerging Systems-on-Chip (SoC) technologies is leading to an ever-increasing use of reusable Intellectual Property (IP) cores. It is not at all obvious to dispose of the necessary knowledge for successful design and use of IP cores, together with a system perspective that includes both hardware and software.
Each product follows particular user/customer requests that establish the characteristics necessary for subsequent processing and target applications.
Among important steps, when building your IP block, are the functional verification and operational performance, which are up to the design tool compatibility.
Whether you make the IP Core for yourself or for third parties, a well-conceived IP Core development schedule should include a careful comparative evaluation phase between different options, before selecting the final one, which almost never coincides with the option with the lowest cost or the highest performance. Wrong choices in this phase can lead to serious delays, with design re-elaborations and, therefore, higher costs.
You must also target, during the design and development phase, reusability, in order to make your IP Core as much usable as you and your team or a potential buyer need. This means, indeed, that another fundamental factor in the process is the quantity and quality of the design documentation, which should be accurate, organized and legible. For those who will eventually use your IP Core, the documentation is the essential key for understanding its functionality and interface. For you, instead, it means guaranteeing, at any time, the possibility to update your IP Core, to solve the technical problems that you will certainly encounter during development, integration and testing.
These aspects are accompanied, with equal importance, by the ability to implement the best technical solution on the specifications set. In this context, TEDIEL offers consolidated experience in design of tailor-made architectures for FPGA and SoC devices.